The following issues in combination make packet buffering particularly difficult at 40 Gbits/s line rates:
1. High data bandwidth is required to accommodate the simultaneous reading and writing of packets (at worst case fabric overspeed).
2. High address bandwidth is required to cope with the worst case whereby streams of minimum sized packets are simultaneously being written to and read from the memory in a random access mode.
3. Memory capacity must be high as buffers will fill up rapidly during transient bursts at high line rates.
4. The manipulation of state which is associated with either logical queue management or memory management must be minimised at high line rates. The number of system clock cycles typically available to the hardware or software device which performs such a function will be minimal.
A solution which places packets directly into queues mapped into statically assigned memory can meet (2) and (4) but uses memory inefficiently and therefore fails on (3). A solution which buffers packets in on-chip memory or SRAM will be able to meet (2) but not (3) since SRAM is a low capacity memory. Implementing a solution which uses high capacity DRAM will be able to meet (3) but will have difficulty in meeting (2) as the random access time is small. In attempting to meet (1), solutions need to implement high bandwidth interconnects and high pincount interfaces.
Overall, it is very difficult to design architectures that meet all four criteria.